As the processing speed of computers increases, the need for faster access to instructions and data increases correspondingly. Reducing the delay time, T.sub.aoe, between the initiation of an output enable command signal and the commencement of data output onto a system bus facilitates faster data access.
Concomitant with faster output data rates is the problem of noise generation. Noise, or bounce, on the power supply and ground lines can be generated by reactive loads coupled to the output drivers and the power supply and ground lines.
Various implementations of output enable control circuits have been developed with these two considerations in mind. See for example, Gubbels et al, "A 40-ns/100-pF Low-Power Full-CMOS 256K (32K.times.8) SRAM," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, p. 741, Oct. 1987; Gabara et al, "Ground Bounce Control in CMOS Integrated Circuits," Int'l Solid-State Circuits Conference, p. 88, 1988; Wang et al, "A 21-ns 32K.times.8 CMOS Static RAM with a Selectively Pumped p-Well Array," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, p. 704, Oct. 1987; Canepa et al, "A 90 ns 4Mb CMOS EPROM," Int'l Solid-State Circuits Conference, p. 120, 1988; and Wada et al, "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, p. 727, Oct. 1987.